[{"id":96,"link":"https:\/\/fpgawizard.com\/clock-domain-crossing\/","name":"clock-domain-crossing","thumbnail":{"url":"https:\/\/fpgawizard.com\/wp-content\/uploads\/2025\/04\/cdc_fifo.png","alt":""},"title":"What is Clock Domain Crossing? How to Avoid Metastability?","author":{"name":"yalcin","link":"https:\/\/fpgawizard.com\/author\/yalcin\/"},"date":"Jul 13, 2025","dateGMT":"2025-07-13 14:26:01","modifiedDate":"2025-07-13 14:26:49","modifiedDateGMT":"2025-07-13 14:26:49","commentCount":"0","commentStatus":"open","categories":{"coma":"<a href=\"https:\/\/fpgawizard.com\/category\/articles\/\" rel=\"category tag\">Articles<\/a>","space":"<a href=\"https:\/\/fpgawizard.com\/category\/articles\/\" rel=\"category tag\">Articles<\/a>"},"taxonomies":{"post_tag":""},"readTime":{"min":13,"sec":31},"status":"publish","content":"What is Clock Domain Crossing? Clock Domain Crossing (CDC) refers to the act of transferring signals or data between two logic regions that are driven"}]
